Overview of Swallow --- A Scalable 480-core System for Investigating the Performance and Energy Efficiency of Many-core Applications and Operating Systems

We present Swallow, a scalable many-core architecture, with a current configuration of 480 x 32-bit processors. Swallow is an open-source architecture, designed from the ground up to deliver scalable increases in usable computational power to allow experimentation with many-core applications and the operating systems that support them. Scalability is enabled by the creation of a tile-able system with a low-latency interconnect, featuring an attractive communication-to-computation ratio and the use of a distributed memory configuration. We analyse the energy and computational and communication performances of Swallow. The system provides 240GIPS with each core consuming 71--193mW, dependent on workload. Power consumption per instruction is lower than almost all systems of comparable scale. We also show how the use of a distributed operating system (nOS) allows the easy creation of scalable software to exploit Swallow's potential. Finally, we show two use case studies: modelling neurons and the overlay of shared memory on a distributed memory system.Comment: An open source release of the Swallow system design and code will follow and references to these will be added at a later dat

Scalable data abstractions for distributed parallel computations

The ability to express a program as a hierarchical composition of parts is an essential tool in managing the complexity of software and a key abstraction this provides is to separate the representation of data from the computation. Many current parallel programming models use a shared memory model to provide data abstraction but this doesn't scale well with large numbers of cores due to non-determinism and access latency. This paper proposes a simple programming model that allows scalable parallel programs to be expressed with distributed representations of data and it provides the programmer with the flexibility to employ shared or distributed styles of data-parallelism where applicable. It is capable of an efficient implementation, and with the provision of a small set of primitive capabilities in the hardware, it can be compiled to operate directly on the hardware, in the same way stack-based allocation operates for subroutines in sequential machines

Design of 370-ps Delay Floating-Voltage Level Shifters With 30-V/ns Power Supply Slew Tolerance

A new design method for producing high-performance and power-rail slew-tolerant floating-voltage level shifters is presented, offering increased speed, reduced power consumption, and smaller layout area compared with previous designs. The method uses an energy-saving pulse-triggered input, a high-bandwidth current mirror, and a simple full latch composed of two inverters. A number of optimizations are explored in detail, resulting in a presented design with a dVdd slew immunity of 30 V/ns, and near-zero static power dissipation in a 180-nm technology. Experimental results show a delay of below 370 ps for a level-shift range of 8-20 V. Postlayout simulation puts the energy consumption at 2.6 pJ/bit at 4 V and 7.2 pJ/bit at 20 V, with near symmetric rise and fall delays

A 6.7-GHz Active Gate Driver for GaN FETs to Combat Overshoot, Ringing, and EMI

Active gate driving has been demonstrated to beneficially shape switching waveforms in Si-and SiC-based power converters. For faster GaN power devices with sub-10-ns switching transients, however, reported variable gate driving has so far been limited to altering a single drive parameter once per switching event, either during or outside of the transient. This paper demonstrates a gate driver with a timing resolution and range of output resistance levels that surpass those of existing gate drivers or arbitrary waveform generators. It is shown to permit active gate driving with a bandwidth that is high enough to shape a GaN switching during the transient. The programmable gate driver has integrated high-speed memory, control logic, and multiple parallel output stages. During switching transients, the gate driver can activate a near-arbitrary sequence of pull-up or pull-down output resistances between 0.12 and 64 A hybrid of clocked and asynchronous control logic with 150-ps delay elements achieves an effective resistance update rate of 6.7 GHz during switching events. This active gate driver is evaluated in a 1-MHz bridge-leg converter using EPC2015 GaN FETs. The results show that aggressive manipulation of the gate-drive resistance at sub-nanosecond resolutions can profile gate waveforms of the GaN FET, thereby beneficially shaping the switch-node voltage waveform in the power circuit. Examples of open-loop active gate driving are demonstrated that maintain the low switching loss of constant-strength gate driving, while reducing overshoot, oscillation, and EMI-generating high-frequency spectral content

Clinicopathological Determinants of Recurrence Risk and Survival in Mucinous Ovarian Carcinoma

Mucinous ovarian carcinoma (MOC) is a unique form of ovarian cancer. MOC typically presents at early stage but demonstrates intrinsic chemoresistance; treatment of advanced-stage and relapsed disease is therefore challenging. We harness a large retrospective MOC cohort to identify factors associated with recurrence risk and survival. A total of 151 MOC patients were included. The 5 year disease-specific survival (DSS) was 84.5%. Risk of subsequent recurrence after a disease-free period of 2 and 5 years was low (8.3% and 5.6% over the next 10 years). The majority of cases were FIGO stage I (35.6% IA, 43.0% IC). Multivariable analysis identified stage and pathological grade as independently associated with DSS (p p < 0.001). Grade 1 stage I patients represented the majority of cases (53.0%) and demonstrated exceptional survival (10 year DSS 95.3%); survival was comparable between grade I stage IA and stage IC patients, and between grade I stage IC patients who did and did not receive adjuvant chemotherapy. At 5 years following diagnosis, the proportion of grade 1, 2 and 3 patients remaining disease free was 89.5%, 74.9% and 41.7%; the corresponding proportions for FIGO stage I, II and III/IV patients were 91.1%, 76.7% and 19.8%. Median post-relapse survival was 5.0 months. Most MOC patients present with low-grade early-stage disease and are at low risk of recurrence. New treatment options are urgently needed to improve survival following relapse, which is associated with extremely poor prognosis